This invention relates to a data reproduction system, a data reproducing method, and a computer program therefor and, in particular, to the data reproduction system, the data reproducing method, and the computer program capable of reproducing high-quality image while preventing occurrence of jerkiness in the course of reproduction processing of content under a varied reproducing speed, e.g., under a high speed or a low speed.
Most of the hard-disc recorders, DVD recorders, or other data reproducing devices of late allow users to set a desired reproducing speed, such as high-speed reproduction or slow-speed reproduction, in reproducing the content recorded in hard-disc, DVD, or other recording media.
Generally practiced high-speed reproduction by the data reproduction equipment in the past is to decimate the data, in other words, to omit some out of the all frames composing a moving image content, one frame each at regular intervals, then processing the rest of frames after such decimation for showing on the display. When shown on the display, however, the image data with decimated frames is apt to produce unnatural movement, as in the example case of displaying an object moving at a constant speed. Such unnaturalness takes the shape of so-called saccadic movement or jerkiness in movement.
With reference to FIG. 1, the mechanism of causing jerkiness is explained. FIG. 1 is a drawing to explain about the mechanism on how the deterioration in motion of image, as is commonly called “jerkiness,” is generated.
It is assumed that a high-speed reproduction is made of temporally successive frames 1 through 12 shown in FIG. 1(a). Each of the frames 1 through 12 includes a moving object 11. This moving object 11 moves downward as the frame changes to new one after another from 1 toward 12. FIG. 1(b) is a drawing of only the vertical lines of the image region including the object 11 laid out in the order of frames 1 to 12. One vertical cell means one pixel. The moving object 11 moves downward by one pixel for each frame-to-frame transfer.
When this image data is reproduced at a high speed, decimation of frames is executed. It is assumed here that frames 3, 6, 9, and 12 be omitted at the time of reproduction. The reproducing speed will become 1.5 times (3/2 times) as much. Thus, the image reproduced will be made up like 1, 2, 4, 5, 7, 8, 10, and 11 in the order of frames, while frames 3, 6, 9, and 12 are not reproduced.
As is understandable from FIG. 1(c), the moving object 11 moves by one pixel between the reproduced frames 1 and 2, but it moves by 2 pixels between the reproduced frames 2 and 4. In a high-speed reproduction, reproduction processing is carried out at even intervals in terms of time and in the order of frames 1, 2, 4, 5, 7, 8, 10, and 11. As a result, viewers will observe that the moving object 11 will show an unnatural behavior of repeating quick and slow movements. This is the phenomenon so-called “jerkiness” meaning that the object displayed will show jerky motions here and there. The main cause for generating jerkiness lies in the decimation processing of reproduction frames.
Some ideas have been presented concerning data reproduction systems in which reproducing speed is made variable. For example, Japanese patent Laid-Open publication (JP-A, hereinafter) No. 1995-303240 refers to one of such data reproduction devices, and explanation thereof is given as follows referring to FIG. 2. This data reproduction device has a data storage section 101 with HDD etc., a decoding section 102, a buffer control section 103, a buffer memory 104, an output control section 105, a display section (monitor) 106, an input section 107, and a system clock 108.
In the data storage section 101 with HDD etc., the image data as the object for reproduction is stored in the form of compressed image data such as MPEG image data. The decoding section 102 processes decoding of MPEG data, for example. The decoded data is temporarily stored in the buffer memory 104 under control of the buffer control section 103 and then outputted to the display section 106 made of LCD etc., as a monitor under control of the output control section 105.
Reproducing speed is set as desired by the user through the input section 107. The data regarding the reproducing speed setting inputted through the input section 107 is forwarded to the internal counter 109 of the decoding section 102. In the device shown in FIG. 2, a fixed clock signal is inputted from the system clock section 108 to the data storage section 101, the decoding section 102, the buffer control section 103, the buffer memory section 104, the output control section 105, and the display section 106, and thus, the inputted clock signal is to control timings of processing at each section.
The clock 109 in the decoding section 102 counts the value of the counter operating on the clock supplied by the system clock 108. Based on this value of the counter, the timing of the processing to be executed is defined. In the case of MPEG2, for example, the packet the image data is stored in is provided with a time stamp that specifies the timing of processing. For example, PTS (Presentation Time Stamp), DTS (Decoding Time Stamp), SCR (System Clock Reference), etc., are adopted, each being described by the time unit of 90 kHz clock pulse. The specification for each of PTS, DTS, or SCR is set for 33-bit description to fit for 24 hours, but for the clock actually used in the decoder, a lower-bit counter (for example, a 32-bit counter) may as well be applied.
The clock 109 in the decoding section 102 counts the value of the counter operating on the clock pulse supplied by the system clock 108 to decide on the timing of processing to be executed in the decoding section 102 and carry out decoding processing. By such control of processing timing, adjustment is made of the output time for the video and audio data to be outputted from the decoding section 102.
The decoded image data outputted from the decoding section 102 is temporarily stored in the buffer memory 104 under control of the buffer control section 103 and then outputted to the display section 106 made of LCD etc., as a monitor under control of the output control section 105. Each of these sections has the processing timings defined by the clock pulse supplied from the fixed system clock 108 to execute processing.
The frame data to be outputted from the decoding section 102 is to be outputted according to the timings specified in the reproducing speed setting data inputted at the input section 107. But the processing timings at the buffer control section 103, the buffer memory 104, the output control section 105, and the display section 106 are defined by the clock pulse supplied by the system clock 108 which is a fixed clock pulse not to be changed irrespective of reproducing speed. Therefore, even if the frame data to be outputted from the decoding section 102 is outputted at shorter intervals than normal, processing at the buffer control section 103, the buffer 104, the output control section 105, and the display section 106 can be conducted only at the same timings as the normal reproducing processing. For example, processing is conducted according to a frame rate of 60 frames a second, that is, the normal speed of reproduction.
Therefore, it happens that processing speed cannot keep pace with the full number of frames to be outputted from the decoding section 102, resulting that the display will be made up of not all the image frames but with some frames lacking at intervals. Consequently, the high-speed reproduction data to be shown on the display section 106 will turn out to be an image with which some jerkiness mingles together, as explained above in reference to FIG. 1.
JP-A-2004-56761 includes an embodiment disclosing how to solve the problem of jerkiness. Disclosed in this JP-A-2004-56761 is a reproduction system that has a configuration to supply a variable system clock pulse to an output control section executing output control for image data to be sent to a display section.
As shown in FIG. 3, the above reproduction system includes a data control section 101 with HDD etc., a decoding section 102, a buffer control section 103, a buffer memory section 104, an output control section 105, a display section 106, an input section 107, and a system clock 108. In FIG. 3, the same sections as appearing in FIG. 2 are shown given with the same reference numbers. The configuration shown in FIG. 3 further includes a variable system clock 111 for supplying the clock pulse to the output control section 105, and a buffer memory 112 attached to the output control section 105.
The data storage section 101 made of HDD etc., stores the image data as the object for reproduction in the form of compressed image data such as MPEG image data. The decoding section 102 carries out, for example, MPEG data decoding processing. The decoded data, after temporarily stored in the buffer memory 104 under control of the buffer control section 103, is outputted to the display section 106 as a monitor and made of LDC etc., under control of the output control section 105.
In the configuration shown in FIG. 3, a variable clock is inputted to the output control section 105 that performs output control for the image frame data to be outputted to the display section 106. This enables the timings variable, namely the timings of inputting image frame data to the output control section 105 and also of outputting image frame data from the output control section 105 to the display section 106. In order to adjust input and output of data in case of any disagreement of timings, there is provided the output control section buffer memory 112 in which it is made possible to keep a buffering accumulation of data in case the input data is excessive as compared to the output data.
The above configuration permits the output control section 105 to do processing according to its own variable system clock 111 and also to alter reproduction frame rate at the display section 106. For example, it becomes possible to display image not only at a normal frame rate of 60 frames per second but also at a faster frame rate such as 90 frames per second.
If display is made at such a frame rate, high-speed reproduction does not necessarily require decimation of frames as explained hereinabove with reference to FIG. 1, but it becomes possible to display all the image frames at shorter time intervals than the intervals of a normal reproduction. As a result, the problem of jerkiness arrives at a solution.
The configuration shown in FIG. 3, however, requires that the output control section buffer memory 112 be provided for data output and input adjustment at the output control section 105.
Further in the case of the configuration shown in FIG. 3, changing the reproducing speed while a certain moving image content is being reproduced at a certain reproducing speed, for example, will entail change in setting of the supply clock of the variable system clock 111. In this case, only the input clock to the output control section 105 is to be changed necessitating synchronizing the input clock to the sections preceding to the output control section 105 with the changed clock to the output control section 105, and since a time-lag takes place as it takes time to execute such synchronization, there occur such problems that the processing at the output control section 105 is obliged to halt temporarily and that the display processing at the display section 106 is also compelled to be interrupted.